Subsystem Verification & Analysis of Intellectual Property of Arm® Cortex®-A65AE Architecture

Abstract

The development of autonomous vehicles is accelerating rapidly, creating significant challenges for advancing integrated circuits within the automotive sector. One primary challenge is ensuring devices' functional safety without relying on backup or redundant circuits. Verification involves comparing a product’s design against its specifications to ensure that the design and the produced items meet customer requirements and can be reliably delivered. Errors, which occur randomly and can originate from various modules on the SoC, must be meticulously managed to prevent potentially life-threatening situations. This study presents the IP alongside its verification process and coverage analysis. Verification teams face obstacles in verifying bus performance due to increasing design complexity and constrained development timelines. They need faster execution times, straightforward test bench creation, and efficient test pattern generation. Renesas encountered similar challenges in assessing bus performance in their chips, particularly in latency and bandwidth over time. To address these issues, Renesas utilized Cadence tools and implemented operational flows integrating AVIP and ATP, employing Palladium to reduce prolonged emulation times. The Arm Cortex A65AE Architecture is a power-efficient, mid-range, throughput-oriented, Simultaneously Multithreaded (SMT) architecture that implements the AArch64 execution state of the Armv8-A architecture within the Dynamic IQ Shared Unit (DSU) cluster. It does not implement the AArch32 execution state of the Armv8-A architecture. As an SMT core, the Cortex A65AE supports two execution threads per core, with each thread functioning as a separate architectural Processing Element (PE) and maintaining a complete copy of the architectural state. This simultaneous multithreading allows the Cortex A65AE to issue and execute instructions from both threads concurrently within the same cycle. Software perceives a thread on the Cortex A65AE, in the same way, it views a core in a traditional single-threaded, multi-core processor, enabling existing software for single-core and multi-core systems to run unmodified on the Cortex A65AE Architecture.