Analysis and Design of 14-Bit Self Calibrated DAC of SAR-ADC for Bio-Medical Application

Abstract

SAR-ADC is best suited for low power applications where power has a trade-off with speed. Use of redundant circuitry reduces the on chip area making it cost effective. DAC is one of the components of SAR-ADC that introduces error voltage due to mismatch and consumes large power other than comparator. This work presents the analysis and design of the high resolution i.e. 14-bit Digital to Analog convertor (DAC) which is Self Calibrated for the capacitive mismatches. DAC that has been designed is a smart circuit which performs three operations consecutively they are sampling, subtracting voltages and digital to analog conversion. All this work is primarily focused for the Bio-Medical Applications and hence the operational parameters are selected accordingly. Sampling speed of DAC is 100kS/s i.e. very slow speed as we have a tradeoff with power here in this operational circuit design. 1.6 MHz clock speed is used for the analysis of the DAC. Proposed DAC uses self calibration technique which is a foreground calibration technique and is used for calibrating maximum of 20fF capacitance mismatch which is greater than the mismatch equivalent to LSB (Least Significant Bit) capacitor. Power for each conversion cycle is calculated which is very less in the order of nWatt and gain error is less than 0.5LSB. EDA tool used for design and analysis is Cadence® Virtuoso Analog Design Environment with 180nm technology and Cadence® Virtuoso Layout XL Environment for designing and verification of layouts.