Surface Potential Based Drain Current Modeling of Junctionless Double-Gate MOSFET

Abstract

The Junctionless transistor is a device with uniform doping concentration in the channel and source/drain regions. This change in device structure poses many advantages like simplified fabrication process, nearly ideal subthreshold slope, high on to off current ratio, lower DIBL effect etc. In this dissertation, a surface potential based drain current model has been developed for long channel junctionless double gate MOSFET. The threshold voltage model has also been developed. For each region of operation of the device i.e. depletion, partial depletion and accumulation, a different model has been developed and then merged for the entire range of gate voltage. Effect of various geometrical parameters like channel length, silicon thickness, oxide thickness and doping concentration on surface potential and drain current has been studied. Effect of drain voltage on the threshold voltage has exclusively been studied. Surface potential has been calculated in terms of the Lambert W function for subthreshold region. Surface potential model has been used further to calculate mobile charge density in the channel region and Pao-Sah integral has been used to calculate drain current of the device. Simulation of the device has been performed using Silvaco ATLAS tool. Developed model has been compared with the published and simulation results, and they are in good agreement with each other.