Design of CMOS Current Conveyors for Analog VLSI

Abstract

Current conveyor is a high performance analog circuit design block based on current mode approach. It is basically a unity gain element that exhibits high linearity, wide dynamic range, high bandwidth and better high frequency performance. The current conveyor is a combination of voltage as well as current follower. The second and third generation current conveyors, based on translinear loop, having voltage and current gain closer to unity are presented in this thesis. The main feature of these current conveyors is their high voltage and current transfer bandwidth which make them suitable for high frequency applications. The current conveyors are simulated using UMC 0.35μm CMOS 1P6M process parameters with power supply of ±1.5V in Cadence® Virtuoso Analog Design Environment. Layouts of the circuits have been designed in Cadence® Virtuoso XL Design Environment. The post-layout simulations at different process corners along with temperature and supply variations have been presented to validate the performance of these current conveyors.