ATPG Pattern Generation and Simulation for Enhanced Fault Coverage with DFT Flow

Abstract

As the complexity of Very Large Scale Integration (VLSI) circuits continue to escalate, ensuring their reliability and correctness has become a paramount challenge. Manufacturing defects, even minor ones, can lead to complete system failure, making robust testing an indispensable part of the semiconductor production cycle. This thesis ad- dresses the critical need for efficient testing methodologies through the exploration of Design for Testability (DFT). The primary objective of this research is to develop and simulate Automatic Test Pattern Generation (ATPG) strategies to achieve enhanced fault coverage in complex digital circuits. The work begins with a comprehensive review of fundamental and advanced DFT techniques, including scan design, scan compression, and various fault models such as stuck-at and transition faults. The proposed methodology follows a structured DFT flow, starting from Register- Transfer Level (RTL) design and proceeding through synthesis and DFT insertion. This involves integrating testability structures like scan chains and BIST logic directly into the design to improve the controllability and observability of internal nodes. The core of the work focuses on leveraging these DFT structures for effective ATPG and simulating the generated patterns to validate their effectiveness in detecting manufacturing faults. The research aims to contribute to reducing test time and improving the overall quality and reliability of VLSI products.