Integrated Approach to Supply Noise Reduction In Advanced IC’s and Die Package Board Ripple Analysis

Abstract

Supply noise is a major challenge in advanced integrated circuits (ICs) that can degrade performance and reliability. This work addresses the important problem of supply noise reduction using Decoupling Capacitors (Decaps), SHDMIM (Super High-Density Metal Insulator-Metal) capacitors and Power Grid (PG) fills. With the scaling down of the IC technology and increasing operating frequencies, the stabilization of power supply voltages becomes crucial for proper functioning of the circuit. A complete methodology for accurate estimation and allocation of Decaps and SHDMIM capacitors in IC design is developed using Redhawk-SC tool. This methodology seeks to reduce voltage fluctuations, a major source of supply noise, thereby improving signal integrity and reducing the chances of logic failures. Further, SHDMIM capacitors are complemented with the incorporation of PG fills, which ensures robust power delivery and minimizes the voltage drops in both static and dynamic conditions. This concurrent approach guarantees that the implementation of SHDMIM capacitors and PG does not deteriorate other important parameters such as power consumption and propagation delay. The results shows the need of efficient supply noise suppression methods in advanced ICs and provide useful guidelines to IC designers for better performance and reliability. The analysis reveals that the considerable reduction in voltage fluctuation from 140 mV to 70.5 mV and reduction in settling time from 13.5 to 5.5 ns which results in improved circuit performance with greater signal integrity, lesser error rates and higher reliability. This work provides a detailed analysis and practical implementation strategy demonstrating the potential of SHDMIM capacitors and PG fills as important building blocks to realize noise free, high performance integrated circuits. The present work opens the door to future advances in IC design and optimization.

The proposed methodology involves the generation of Chip Power Model (CPM), which records the dynamic switching current profile of the integrated circuit over a transient window of 1000 ns. This active die model is embedded into a complete co-simulation environment to enable a realistic model of the power supply noise. The specific impedance characteristics of the IC Package and PCB are represented by Parasitic netlists imported using the Chip Model Analyzer tool. Accurate port connections are made to ensure a continuous electrical path to the active transistors from the voltage regulator.

The study gives the magnitude of the time domain voltage fluctuations (ripple) caused by the coupling of the on-chip switching activity with the off-chip parasitic inductance using transient analysis. The results demonstrate that this Die Package-Board co-analysis provides significantly more accurate ripple estimation compared to standalone simulations. This approach enables early identification of Power Delivery Network (PDN) weaknesses so that required amount of voltage to be reached to the die which will meets the timing and will not result in logic failure. It has been noted that the voltage ripple between Package Node 1 and PCB is 40 mV in 70 ns period of time, the voltage ripple between PCB Ports (16 to 2 ) is also 40 mV in 70 ns period of time and the voltage ripple between Package Node 2 and Die is 174 mV in 70 ns period of time.