Modelingof Drain Current for Lightly Doped Symmetrical Double Gate MOSFETIncluding Short Channel Effects

Abstract

Symmetrical double gate has become one of the preferable choices for scaling CMOS devices down to nanometer size as they have excellent control over short channel effects and provide lower gate leakage current, higher on-current and better subthreshold slope reduction. Several analytical surface potential and charge based drain current models has been proposed earlier for DG MOSFETs but the development of anappropriate analytical drain current model for nano-MOSFETs is still under research. In this thesis, a drain current model for lightly doped symmetrical DG MOSFET in sub-nanometer regime is presented by considering weak and strong inversion regions including short channel effects, series source/drain resistance and channel length modulation parameters. This two dimensional-potential-distribution based drain current model alsoincludes the effects of subthreshold slope and threshold voltagevariations. Lastly the effect of the fixed oxide trap charges on the drain current has been studied and evaluated. Further, for 32 nm and 45 nm technologies the current-voltage characteristics of drain current model for DG-MOSET are compared and validated with the simulation resultsforall regions of its operation and SILVACO (Atlas) TCAD tool is used for simulation.The series source/drain resistance effect has also been studied in C-V characteristics. From the above results it is found that the model and the simulation results are in good agreementfor devices having channel length to silicon film thickness ratio greater than or equal to 2. Subthreshold slope and threshold voltage models are also compared with simulation results at different channel lengths and silicon film thickness.Finally, the fixed-oxide trap charge effect on drain current for different gate voltages shows remarkable agreement for large range of its value but starts showing deviation with the simulation results at its very high values.