Automated Power Switch Stiching Using Daisy Chain Methodology

Abstract

Power switch stitching is a critical aspect of power management in modern VLSI design, ensuring efficient power distribution across various power domains within an integrated circuit. This report explores the methodology of power switch stitching using a daisy chain approach within the Cadence Automatic Placement and Routing (APR) construction flow, which is essential for achieving robust power management in complex designs. The flow leverages Cadence's Genus tool for design elaboration and Design-for-Test (DFT) insertion, followed by Innovus for detailed physical implementation, including stages such as floorplanning, power planning, clock tree synthesis (CTS), post-CTS optimization, routing, and sign-off verification. A key focusis placed on the power planning stage in Innovus, where the Unified Power Format (UPF) file plays a crucial role in defining the power intent, specifying the power domains, voltage levels, and power switches that manage the transition between on and off states. The UPF-based power plan guides the placement of power switches and the subsequent stitching of these switches into a coherent network that ensures reliable power distribution throughout the chip. The daisy chain methodology is employed in the stitching of power switches to simplify the control and management of multiple power switches across different power domains. This method reducesthe complexity of wiring by connecting switches in a sequential manner, ensuring proper timing and control over the power delivery. The report delves into the intricacies of implementing this approach, examining how it enhances the efficiency of power gating and ensures consistency in power distribution across the integrated circuit. By integrating the daisy chain approach into the power switch stitching process, this methodology offers a streamlined solution for managing power transitions in advanced VLSI designs, ensuring a balance between performance and power efficiency.