Design and Implementation of an Optimized Viterbi Decoder

Abstract

The vision of wireless communication providing high-speed and high-quality information exchange between two portable devices located anywhere in the world is the communications frontier of the current century. In this busy and unsecure world you need to be sure your data is not only safe and secure but that you are working with it at the highest speed possible. Convolutional encoding is a forward error correction technique that is used for correction of errors at the receiver end. Viterbi decoding is the technique for decoding the convolutional codes. The Viterbi Algorithm, an application of dynamic programming, is widely used for estimation and detection problems in digital communications and signal processing. It is used to detect signals in communications channels with memory, and to decode sequential error control codes that are used to enhance the performance of digital communication systems. The Viterbi decoding algorithm is widely used in radio communication: digital TV (ATSC, QAM, DVB-T, ), radio relay and satellite communications. This thesis represents the implementation of 3-bit soft decision viterbi decoder of constraint length K=7 with a code rate (R) of ½ and its algorithm. The decoder architecture is defined in VHDL and the circuit is simulated and synthesized on Xilinx: XC3S500E-4FG320 FPGA device. Frequency of soft decision viterbi decoder has been increased by using pipelining. Also puncturing technique is implemented in matlab to verify different transmission code rates. The plots of simulation results of bit error rate (BER) with different code rates are obtained from matlab code.