Design and Analysis of Smart Voltage Comparator

Abstract

Digital wireless communication, digital signal processing and implanted biomedical devices have emerged as exciting applications of Analog-to-Digital Converters (ADCs). All these applications are energy-constrained and thus demand low-power ADCs. A comparator is a key building block in ADC architecture. Its design affects the various parameters of ADC like power consumption, delay, accuracy etc. An efficient comparator detects the small input voltage difference within short time and amplifies the output to either of the two logic levels i.e. 0 or 1. This work proposes a novel, digital-in-concept and opamp-less approach to design a fully-differential voltage comparator. Besides low power consumption, it is highly cost-effective as an analog circuit has been designed digitally. Comparators are designed and simulated in Cadence® Virtuoso Analog Design Environment using UMC 180nm CMOS digital process at 1.8V supply with load capacitance of 1pF. Layout of the proposed comparator was designed in Cadence® Virtuoso Layout XL Design Environment. The post-layout and process corner simulations were done for the propagation delay, offset voltage and average power dissipation.