Low Power Memory Cell Design

Abstract

Static Random Access Memory (SRAM) has been widely utilized as the representative memory for very large scale integrated (VLSI) circuits. This is because SRAM belongs to faster technology in comparison with the previously reported technologies. However, the power consumption in SRAM is relatively high. Therefore, it is important to reduce the power consumption in SRAM cell as it plays a significant role in the memory design. The main objective of this thesis is to provide new and efficient ways to design a low power SRAM cell. This work proposes the new techniques for SRAM cell design based on seven transistors (7T) and introduces various circuit topologies and techniques to calculate leakage current, delay and power. The area and cell stability of SRAM are taken care of while optimizing the power reduction. During the research, the Half-selected cell stability of 7T SRAM cell was found to be in between 5T and 6T SRAM cells using the Wordline Voltage Control Technique. The use of an additional transistor in 7T SRAM cell structure allows read operation without disturbance as compared to the previously proposed SRAM cells. The 7T SRAM cell has very low power consumption with high Static Noise Margin (SNM) and enhanced read/write stability under large variations. With the process variation methods the gate leakage current of 1.154pA and sub-threshold current of 13.139 pA are obtained whereas read and write SNM of 520mV and 545mV are respectively achieved.