Digitally Enhanced Smart Analog Circuits

Abstract

Today, analog and digital VLSI design has advanced to newer levels. The big challenge of VLSI design lies in minimizing the circuit overhead in terms of silicon area, power consumption and delay. Smart analog circuits are, thus, being looked into to derive the advantages of both, the digital as well as analog world. Smart data converters make use of auxiliary analog and digital circuitry to enhance the features and to eventually tailor the converter architecture for more efficient performance. This work proposes an innovative, digital-in-concept prospective idea for designing smart analog circuits, operated on low voltage. The mixed signal circuit consists of both digital and analog circuit in which the CMOS digital circuit is easier to fabricate and it increases the speed of the circuit as most of the delay in the circuit comes from the analog circuitry. As a demonstration of the strength of smart analog circuits, a low power high speed digitally enhanced flash ADC has been designed. In present work, firstly, digitally enhanced analog voltage comparator has been designed using a pure digital differential circuit technique which is used as basic building block of flash ADC. The proposed digitally enhanced analog voltage comparator circuit has low power dissipation of 0.324μW, high resolution of 1.96mV, low DC offset of 1mV, full output swing of 0-1.8V and common mode input range of 0-1.8V. The circuit has been simulated using SPICE in TSMC of 0.18μm CMOS technology at 1.8V with load capacitance of 1pf.