Implementation of Low Power Viterbi Decoder on FPGA

Abstract

Convolutional encoding is a forward error correction technique that is used for correction of errors at the receiver end. The two decoding algorithms used for decoding the convolutional codes are Viterbi algorithm and Sequential algorithm. Sequential decoding has advantage that it can perform very well with long constraint length. convolutional codes, but it has a variable decoding time. Viterbi decoding is the best technique for decoding the convolutional codes but it is limited to smaller constraint lengths. The basic building blocks of Viterbi decoder are branch metric unit, add compare and select unit and survivor memory management unit. The two techniques for decoding the data are traceback (TB) method and Register Exchange (RE) method. TB method is used for longer constraint lengths but is has larger decoding time. Also extra circuitry is required to reverse the decoded bits. The RE method is simpler and faster than the TB method for implementing the VD. RE method is not appropriate for decoders with long constraint lengths. In this thesis, Viterbi decoder with modified register exchange is implemented. Its specifications are the coding rates 1/3, with the generator polynomial of 171, 165 and 133 respectively and constraint length is 7 with 128 states .The bit serial architecture combined with the modified register exchange method are proposed which reduces the power dissipation. Pointer concept is used for implementing the survivor memory unit of the VD. A pointer is assigned to each register or memory location. The trace-back operation is eliminated in the new architecture, and the amount of memory is reduced. The new Viterbi decoder has efficient memory organization, low hardware complexity and lower power dissipation. Viterbi decoder is implemented on FPGA. FPGAs reprogrammability and high degree of parallelism attracts them for DSP applications. The hardware description language VHDL is used to describe the design. The design is synthesized using Xilinx Project Navigator software and simulated using Model Sim. The design implementation is done on Xilinx Spartan 2E xc2s15-6cs144.