Digital Phase Locked Loop Interface Design

Abstract

The report presents the implementation of Digital Phase Locked Loop (DPLL) Interface Design to configure the DPLL. The ASIC design methodology is used to implement this interfacing module. The flow can improve the design performance and still preserve the efficiency of the standard ASIC design flow. A typical ASIC design flow is composed of two phases. A first phase is called the front end, in which the synthesis from a hardware description language and/or schematic capture is performed, followed by time and area optimization. This is the logic design step, and it is made as much technology independent as possible. The second phase, called the back end, is the physical design of the circuit; it consists of the placement of all of the components on the core, followed by the routing of the power and signal wires. Obviously, this phase is strongly technology dependent. The hand-crafted fullycustom application-specific integrated circuit (ASIC) design methodology usually deliveries chips with lower power consumption, 5 to 8 times higher speed and more compacted chip layouts than conventional standard ASIC design method. On the other hand, automatic standard ASIC design flow enables more efficient design process. Based on pre-characterized and silicon verified standard cells, the emerging of design automation technology enables standard ASIC have many advantages over full custom designs, such as fast-turn-around time, less design resource requirement, especially human resources, easy for technology migration, high productivity, and thus low price.