Analysis and Design of Robust Power Double Implanted Mosfet on 6H Silicon Carbide Wafers

Abstract

Silicon Carbide is a wide energy gap semiconductor that possesses a combination of parameters that make it ideal for various applications in electronic industry. Its physical properties such as high electric field strength, high saturation drift velocity and high thermal conductivity has placed SiC at the center of renewed focus of semiconductor material and device research amongst other wide energy gap semiconductors. SiC has tremendous advantages because of rapidly maturing technology for making single crystal substrates. In addition, the ability to form a layer of thermal SiO2 on SiC in a similar way to provide the fabrication of Silicon Carbide MOS-based electronic devices. Thus, given the superiority and success of MOS-based devices in applications like high power/temperature electronics and storage devices (nonvolatile memories), SiC is perceived to be the semiconductor of choice with potential to revolutionize the way the electronic systems are designed. In view of current study of power switching devices, the large efforts are concentrated on unipolar devices. These include Field Effect Transistors (FETs) that exist in many types, JFET, MOSFET and MESFET. In low power electronic applications that require high switching speed, the Si MOSFETs have become the dominant technology for many reasons. The relatively low breakdown field in Si and the resistance of drift region that increases rapidly with increasing blocking voltage generally limit the use of Si MOSFETs to 500V and below. The advantages of SiC material properties, in particular breakdown field, makes SiC MOSFETs a very promising candidate for high power switching devices. The specific on-resistance of a SiC power device is expected to be 100-200 times lower than a rated silicon device. Its much lower thermal minority carrier generation implies lower leakage currents and device operation at higher temperatures, arising from self heating due to power dissipation is more tolerable. Moreover, the thermal conductivity of SiC is three times higher than Si and even higher than copper at room temperature. Due to excellent physical and electrical properties such as high breakdown electric field, wide bandgap, high thermal conductivity and high electron saturation velocity, silicon carbide offers great potential for development of high temperature, high power and high voltage devices. Significant progress in SiC power MOSFETs have been demonstrated with the fasbrication of UMOS,DIMOSFET, triple implanted vertical MOSFET and accumulation –mode MOSFET (ACCUFETs). Power MOSFET requires excellent electrical characteristics. Due to these characteristics, it would be desirable to utilize power MOSFETs for high voltage/power electronic applications. However, the blocking capability of a MOSFET is based on the ratings of the reverse body of the diode of the drift region. The blocking voltage is determined in part by the distance from source to drain. High blocking capability implies high resistance because of geometry, so there is a trade off between low drift region resistance values and device voltage capability. The research work carried out here on 6H-Silicon Carbide Double Implanted Power MOSFET has been an attempt to understand the performance of the device with respect to power dissipation and breakdown voltage for various types of doping profiles in the drift region of the device. The doping profiles used are primarily uniformly doped with field dependant and independent mobility, linearly graded, Gaussian and Complementary Error Function distribution. Although a lot of work has been has been described in the literature over the last two decades, no specific work has been reported in which the graded profiles have been used in the drift region of 6H-SiC DIMOSFET for this type of analysis. The ultimate aim for making this study is to provide a graded profile in the drift region of the MOSFET with lower doping at the top of the device to a higher doping near the drain. This type of profile will help in increasing the breakdown voltage while at the same time will reduce the series parasitic resistance at the lower end of the device and thereby reduce the overall specific on-resistance. In this work, we have succeeded in establishing that the power dissipation is minimum in the linearly graded profile evaluated at a current density of 1000 A/cm2, whereas breakdown voltage is maximum of 20kV in the Complementary Error Function profile.