FPGA Implementation of Double Precision Floating Point Square Root with BIST Capability

Abstract

The scope of this work includes study of VERILOG language for computing arithmetic and logical operations and functions suited for hardware implementation, and after that before implementing on FPGA it has capability to test them, i.e. having capability of Built in Self Test. The Double precision floating point square root unit is coded in VERILOG and validated through extensive simulation. This is structured so that they provide the required performance i.e. speed and gate count as well as latency. This VERILOG code is then synthesized by XST (Xilinx synthesis Technology) tool to generate the gate level net list that can be implemented on the FPGA Spartan 3E. The implementations of these designs show that their performances are comparable to, and sometimes higher than, the performances of non-iterative designs based on high radix numbers. The design achieves the Throughput (MFLOPS) 60.16, Latency 9.671ns, and consumes the total X-Power 81(mw). The pipelining of these iterative designs target high throughput computations encountered in some space application, which can be used in doing test calculations like for square root, sine, cosine, etc. which can be utilized in scientific calculations and the main application is the squarer root floating-point unit (FPU) contained in math coprocessor. BIST is beneficial in many ways. BIST can provide at speed, in system testing of the Circuit-Under Test (CUT). This is crucial to the quality component of testing. In addition, BIST overcome pin limitations due to packaging make efficient use of available extra chip area. All these benefits are plentiful motivations for BIST.