Efficient Test Scheduling and IP Mapping Algorithm for NOC Based SOC

Abstract

Advances in semiconductor process and design technology enable the design of complex system chips. Traditional IC design in which every circuit is designed from scratch and reuse is limited to standard-cell libraries, is more and more replaced by a design style based on embedding large reusable modules, the so-called cores. This core-based design poses a series of new challenges, especially in the domains of manufacturing test and design validation and debug. The manufacturing process may result in defected chips, for instance due to the base material, and therefore testing chips after production is important in order to ensure fault-free chips. The testing time for a chip will affect its final cost. Thus it is important to minimize the testing time for each chip. To reduce test cost, SoCs are being increasingly tested in modular fashion, i.e. their various design modules are tested separately. For core-based SOCs this can be done by testing several cores at the same time, instead of testing the cores sequentially. Network on Chip (NoC) architecture with regular topology provide scalable platform for designing System on Chip (SoC) with large number of cores. Designers come across a number of challenges and opportunities while developing products and applications using the NoC architecture. In this thesis report we focus on the various issues faced during the testing of a SoC system. Various schemes have been discussed and implemented to tackle the issues like test time and energy. A genetic algorithm based test solution has been implemented which reduces the test time in a 2D SoC. The application mapping problem has been optimized by using the Particle Swarm Optimization algorithm to reduce the testing time of the application and the energy dissipated during the communication between the cores. First a wrapper design algorithm is developed where the testing time of each core is calculated for a given specific bandwidth. Then a partitioning algorithm is developed to reduce the testing time of the circuit by testing different cores in parallel. The partitioning of cores is done considering mesh based NoC architecture. After partitioning the components of the application circuit, the heuristic algorithms are applied for determining the best floor planning of the cores. The proposed schemes are applied on four benchmark circuits from Duke University, Stuttgart University and Philips and they are d695, g1023, p22810, p93791.