Study of Power Gating Technique for Low Power Flip-Flops

Abstract

Flip-flops are common building blocks and are frequently used in digital VLSI circuits. These are used as starting, ending and intermediate part in delay paths which decides the maximum speed of the systems. They consumes large amount of power because these are operated at system operating frequency. Thus a careful design of low power flip flop with optimum speed is necessary which is becoming challenge with technology scaling. In order to achieve flip-flops power gated technique is used for both single-edge triggered and double-edge triggered flip-flops. Different circuit topologies of flip-flops are used to increase the speed. Static and dynamic flip-flops are studied in order to study optimum tradeoff between power and propagation delay. Different flip-flop designs are simulated in UMC 0.18 µm CMOS process under different

supply voltages in Cadence Analog Design and simulation Environment