FPGA based multiplication using MUX and Vedic Multiplier

Abstract

Most of the algorithms which are used in DSP, image and video processing, computer graphics, vision and high performance supercomputing applications require multiplication and matrix operation as the kernel operation. In this dissertation, we propose Efficient FPGA based matrix multiplication using MUX and Vedic multiplier. The 2x2, 3x2 and 3x3 MUX based multipliers are designed. The basic lower order MUX based multipliers are used to design higher order MxN multipliers with a concept of UrdhvaTiryakbyham Vedic approach. The proposed multiplier is used for image processing applications. It is observed that the device utilization and combinational delay are less in the proposed architecture compared to existing architectures. In this thesis we explore and analyse all the previous work on Floating Point Multiplication. The objective is to design a 32-bit single precision floating point multiplier operating on IEEE 754 standard floating point representations. Second objective is to model the behaviour of floating point multiplier design using VHDL.