Constrained Random Verification of a Digital IP Using System Verilog

Abstract

This thesis describes the restricted random verification of a digital IP for an AXI4-Lite-based design with SystemVerilog. As advanced communication protocols are incorporated into contemporary SoC designs, it is crucial to guarantee the functional accuracy of AXI-compliant intellectual property. Conventional directed testing techniques frequently fall short in covering protocol-level interactions and corner cases. In order to increase coverage, scalability, and reusability, a limited random verification methodology is used. Developing a reusable and modular verification environment with SystemVerilog features like classes, randomization, constraints, assertions, functional coverage, and interfaces is the main goal of the effort. In order to validate address, data, and control channel transactions, an AXIbased digital IP is validated by producing random stimuli within specified protocol limitations. While assertions are used to verify protocol compliance and identify violations during simulation, functional coverage models are used to gauge the completeness of verification. The verification environment is designed to achieve great coverage and to find corner case bugs fast. The efficiency of limited random verification in enhancing design resilience and cutting verification time is shown by simulation results. In order to validate complicated AXIbased digital IPs for dependable SoC integration, this work emphasizes the significance of sophisticated verification approaches.