GENAI POWERED DESIGN VERIFICATION
| dc.contributor.author | Singh, Varsha | |
| dc.contributor.supervisor | Upadhyay, Rahul | |
| dc.contributor.supervisor | Chandwani, Geetanjali | |
| dc.date.accessioned | 2025-08-04T08:21:08Z | |
| dc.date.available | 2025-08-04T08:21:08Z | |
| dc.date.issued | 2025-08-04 | |
| dc.description.abstract | In nowadays changing semiconductor industry, precision is very important for designers, verification engineers, and layout professionals. Due to the high costs and tight schedules involved in chip design, verification, and fabrication, achieving success in first time is important. But this level of accuracy is difficult to get and without a well defined methodology guiding the entire ASIC development process is difficult. Without skilled engineers, rtl design engineers the success in this semiconductor industry is very tough. The increasing design complexity is one of the most major challenge in semiconductor industry nowadays. Many traditional approaches are there but they are very much time taking and inefficient. Compared to the, Artificial Intelligence provides automated and vast number of solutions by reducing manual efforts. After the arrival of GENAI driven techniques, verification process has been made easier and lots of manual efforts have been reduced. This change in semiconductor industry not only increases the verification abilities of engineers but also reduces time required in overall manufacturing cycle to a great extent. | en_US |
| dc.identifier.uri | http://hdl.handle.net/10266/7050 | |
| dc.language.iso | en | en_US |
| dc.subject | Artificial Intelligence | en_US |
| dc.subject | Semiconductors | en_US |
| dc.subject | Chip Design | en_US |
| dc.subject | Verification | en_US |
| dc.subject | Black Box | en_US |
| dc.title | GENAI POWERED DESIGN VERIFICATION | en_US |
| dc.type | Thesis | en_US |
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