Verification and Environment Automation for Debug Optimization of Intellectual Property for Safety IP

Abstract

Verification is the step of aligning a design with the given specifications as per the product requirements. Its primary goal is to ensure that the design of every produced component meets the exact needs of the client. Errors in this process are inherently taken, originating from various modules within the SoC or modules at any time are important to addressing the discrepancies. The IP, as well as its verification process, are presented in this study. The current project on which verification work is done is “Safety IP". This IP works as a source for generating secure pathways and passing them to external ports. The safety IP core module is a unit that controls access to target regions based on configuration access permissions. It interacts with the control unit, a NOC hardware unit that is instantiated within links to interconnected blocks. Taking it as a reference, environment setup is done for AXI/APB protocols using python scripts. As designs become more complex and scale down to the nanometer scale, the problem of debugging becomes more difficult. When the simulation regression is complete, it should fix the reported failures. The process of analyzing and debugging these failures is manual and used more resources. This approach helps automatically classify failures based on their characteristics. Itthen automated the triangulation which determines if failures are in the design or test bench. It uses the dataset to identify errors and divide them into different bins. It then uses these bins to train models to detect and identify errors due to actions that do not complement the original and to trace the root cause of failure in a particular container. The learning model is based on CNN with several abstraction layers and tools used are Cadence Xcelium, Vmanager. It gets the debugging coverage result of 91.9%. Aspects covered are register test cases and repetitive checkers functional test cases.