Design of high speed and low power SRAM decoder

Abstract

This dissertation presents the design of an 8 to 256 line decoder for a 256 x 256 6T SRAM array. Here the objective is to design and compare the speed and power efficient memory decoder. In order to achieve this task firstly, various NAND gate architectures have been designed namely conventional NAND gate, NOR style NAND gate and source coupled NAND gate. These architectures are simulated at 180nm technology node on cadence tool [Appendix B]. For schematic entry cadence composer is used, for simulation Cadence Spectre 5.1.4 1_ISR and for layout Cadence Virtuoso 5.1.4 1_ISR is used and its DRC, LVS and RCX has been done using Cadence Assura 3.2.0. Next, three decoders have been designed using conventional NAND gate(4 to 16), NOR style NAND gate and source coupled NAND 8 to 256 gates and their critical paths have been obtained. The circuit techniques used to reduce the power dissipation and delay have been explored. It has been observed that NOR style NAND gate is 96.34% faster and 93.6 % more power efficient than conventional NAND gate. Source coupled NAND gate has been found to be 96.56% faster and 96% more power efficient than conventional NAND gate and 6.25% faster and 42.86% power efficient than NOR style NAND gate. When these gates are used in decoder designs, it has been observed that source coupled NAND decoder gives the best performance and has better power efficiency as compared to other decoder structures. It has been found that NOR style NAND decoder is 94.4% faster and 67% power efficient, whereas source coupled NAND decoder is 94.6% faster and 81.6% power efficient than conventional NAND gate decoder(4 to 16). As compared to NOR style NAND based decoder, source coupled NAND decoder is 5% faster and 44.2% power efficient. Finally, delay power product obtained for the three decoders are 390µ W- ns, 72.27µ W- ns and 38.64µ W- ns respectively.