A Comparative Study of Delay Analysis for Carbon Nanotube and Copper Based VLSI Interconnect Models

Abstract

On-chip global interconnect is perceived to be a bottleneck in present and future highperformance designs because wire delays are not scaling from generation to generation at the same rate as logic delays. To counteract these detrimental effects, various measures are used such as use of wide wires, insertion of repeaters and employing distributed interconnects. In future development of nanoscale ICs, new materials for interconnects are utilized such as low-k material or low resistivity metals such as copper. However as the diameters of conventional metallic interconnection wires reach the mean free path for electrons, surface scattering from the boundaries of ultra-narrow conductors as well as grain boundary scattering would inhibit electronic conduction in the copper wires to an unacceptable level. Consequently, alternative solutions such as metallic carbon nanotube (CNT) interconnects have been proposed in order to avoid the problems associated with global on-chip wires altogether.

This thesis work analyses the efficacy of using single-walled carbon nanotube bundle instead of copper as an interconnect material for the 45 nm technology node. Various analytical models for equalized on-chip interconnect are used to calculate theoretical delay for these interconnects. SPICE simulations using PTM level 54 model were carried out to validate the findings. A number of parameters such as interconnect length, pitch, repeater size and number of repeaters were optimized to determine the delay performance of these interconnects. The results reflect that CNT show more than 36% time delay saving than copper for less number of inserted repeaters in global interconnects.