Design and Analysis of CMOS Analog Comparators

Abstract

A comparator is the basic component mainly used in analog-to-digital converters. Ideally, it generates an output logic signal as an instant response to the sign of an analog input (voltage or current). Obviously, a real circuit doesn't achieve the ideal function. The most important limits are the finite sensitivity, the offset and the finite speed. All these limitations affect the performance of systems where comparators are used, especially when it is required to achieve high-speed (or a high conversion rate) and high resolution. The open loop, two-stage comparator makes an excellent high gain realization. The characterization of the two stages, open loop comparator illustrates the performance capabilities. The performance of the open loop comparator can be improved by the use of hysterisis to remove the influence of a noisy input signal. Hysterisis can be introduced in internal as well as external circuits of the comparator. All of these use positive feedback. Autozeroing can be used in comparators to reduce the input offset voltage. It is seen that self-biased comparators were always stable in the autozeroing techniques. In many comparator applications, the signal is discrete rather than continuous. So in this case it is possible to use regenerative circuits as comparators. These are comparatively fast. It also uses positive feedback. Unfortunately, the transient response of regenerative circuits is characterized by a positive exponential. Therefore, if input signal is small a long time will be required for the signal to reach the region of the exponential response where the slope is steep. A solution to this is to cascade the latch with a preamplifier. This is what we called a high-speed amplifier. The function of the preamplifier is to quickly build up the input to the latch so that slow rate of rise of the exponential response can be avoided. This has resulted in a comparator capable of operating with slew rate up to 2.28 V/ns and greater. A comparator configuration using differential two-stage open loop comparator as the input stage is realized for high-speed applications. The comparators that can drive large capacitance at the output are the self-biased comparators. The configuration is completely complementary i.e. each n-type device operates in push-pull fashion with a corresponding p-type device. It is self-biased through negative feedback. These two differences result in several performance enhancements desirable in comparator applications. The self-biased comparator architecture is the two folded cascode differential amplifiers acting as load for each other. The self-biasing of the amplifier creates the negative feedback loop that stabilizes the bias voltages. The comparator designed has minimum delay. Gain can be decreased to further reduce the delay. The physical mask layout of any circuit to be manufactured using a particular process must confirm to a set of geometric constraints or rules, which are generally called layout design rules. Using the analog layout techniques of matching transistors and stacked layout one can develop the layout of any analog circuit. A layout of self-biased comparator is developed which works satisfactorily.