Design and Analysis of All Digital PLL for Multi-Frequency Generator

Abstract

Phase-Locked Loops (PLLs) are necessary building blocks of wireless communications, Soc applications, and biomedical appliances as they are responsible for

generating frequencies. The conventional PLL designs employ the LC oscillators, a charge- pump, and low pass filters. Currently, PLL designs must develop accordingly to meet the

increasingly demanding requirements imposed on it by today's (and tomorrows) technology. Traditionally, PLL’s design flow requires circuit techniques and analog intensive process technologies. PLL’s now-days should have low-cost, low-power, improved jitter performance, and reduced noise as imposed by modern technology standards to meet specifications of low power budget and can withstand within the noisy environments of complex system-on-chip (SOC) designs. In addition to it, the low silicon area is another constraint required by the modern demands of VLSI domain. Other than above issues, the conventional PLL design suffers from circuit issues such mismatches, PVT variations, and leakage currents in the nanometer scale of technology. To meet the demands of modern day PLL key requirements, recently digital phase locked loops (DPLLs) with digital methodology and all-digital phased-locked loops (ADPLLs) are preferred over the conventional analog PLL designs especially in nanoscale the CMOS technology. It is due to their configurability, flexibility, scalability, easy portability, and small area. Further digital technology requires a low cost and requires the less design to market time. However, all digital PLL suffers from inadequately more power dissipation due to use of conventional time to digital converter (TDC) and digitally controlled oscillator (DCO) based architectures. Other than these problems, ADPLL also suffers from the quantization noise and periodic jitter issues. In this thesis work, the charge pump PLL is designed using the digital approach. The proposed design achieves low power, low jitter, and fast locking. Further to enhance these parameters, the various ADPLL architectures are proposed. TDC is major source of jitter and power consumption in overall ADPLL design. In this work, 4-bit and 3-bit flash architecture based simple, low power, and low jitter TDCs are proposed. Also in this work, ADPLL-I with 4-bit flash TDC is proposed which achieves power of 6.35 mW and periodic jitter of 6.6 ps. To further enhance the performance parameters, ADPLL-II is designed with 3-bit flash TDC and bang-bang frequency detector. This ADPLL-II architecture achieves the periodic jitter of 1.71 ps and power consumption of 5.9 mW. To achieve a low power and low jitter as compared to ADPLL-I and ADPLL-II, ADPLL-III is designed with background calibration based VCO-II. This design enhances the performance of ADPLL architecture and performance parameters

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are improved. This design achieves a low power of 5.3 mW with little increase in the periodic jitter. The achieved periodic jitter is 1.83 ps. The proposed DPLLs and ADPLLs are designed in the SCL digital 180 nm CMOS technology at supply voltage of 1.8 V. These proposed ADPLL designs are suitable for high speed SoCs, battery operated devices, and wireless transceiver applications.