Effect of Tunneling Conductance on the Performance of Multi Walled Carbon Nanotubes as VLSI Interconnects

Abstract

With the scaling in technology nodes, researchers observed that the resistivity of copper as an interconnect increase resulting in increasing its time delay. Due to these drawbacks an alternative for copper as an interconnect was required. This report studies Carbon Nanotube (CNT) as a suitable alternative for VLSI interconnect. Different fabrication methods for the growth of CNT are discussed. Most of these fabrication approaches prefer MWCNT’s growth over SWCNT; however there is a lack of proper modeling technique for analyzing MWCNT as an interconnect. This report discusses the various parameters of MWCNT as interconnect for global lengths for deep sub micron technology levels. Based on these parameters a multi conductor circuit (MCC) model is derived. As MCC model is quite complex which is difficult to analyze and simulate therefore a derived equivalent single conductor (ESC) model is proposed for simulation. Effect of change in driver size, imperfect contact resistance and load capacitance on propagation delay at global length of 1000μm is discussed. Variation in RLC parameters with increasing length and its impact on propagation delay is also discussed and the obtained results are compared with Copper so as to prove the superiority of MWCNT for global lengths deep sub micron technology levels. The role of repeaters in reduction of delay and the impact of change of Dmin to Dmax ratio onto propagation delay is also studied. Further, to study the effect of intershell tunneling conductance on the resistance and propagation delay, a model is proposed for deriving equivalent resistance by including tunneling conductance. Based on the derived equivalent resistance, previously derived ESC model is modified and simulations are performed for delay analysis. The resistance and propagation delay obtained by considering tunneling conductance are compared with the results without considering tunneling conductance and results are analyzed to observe its effect on interconnect performance. All the calculations and simulations are carried out for 32nm, 22nm and 16nm technology nodes using ITRS 2013 parameters.