Design of Low Power and High Speed Sense Amplifier
| dc.contributor.author | Himanshu | |
| dc.contributor.supervisor | Chatterjee, Arun Kumar | |
| dc.date.accessioned | 2010-08-30T13:03:04Z | |
| dc.date.available | 2010-08-30T13:03:04Z | |
| dc.date.issued | 2010-08-30T13:03:04Z | |
| dc.description.abstract | ABSTRACT The sense amplifier plays an important role to reduce the overall delay and power dissipation of the memory. This thesis work explores the design and analysis of voltage mode sense amplifier and current mode sense amplifier using Mentor Graphics (V2006.4_4.1) at 180nm process technology. The voltage mode sense amplifier circuit has been designed and simulation has been done on Mentor Graphic. A delay of 9.5ns and power dissipation of 243μW was found. Next, the current mode sense amplifier has been designed. From the simulation results it is found that the net delay of sense amplifier is 8.2ns and power dissipation is 0.21μW. This shows a significant improvement in delay and power dissipation in comparison of the voltage mode sense amplifier. The current mode sense amplifier is further designed using a low power and high speed circuit design technique which reduces the power dissipation to 0.073μW. Finally, the layout for voltage mode sense amplifier and current mode sense amplifier have been drawn and layout versus schematic simulation results has been compared. | en |
| dc.format.extent | 617379 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/10266/1203 | |
| dc.language.iso | en | en |
| dc.subject | sense amplifier,Low power techniques, MTCMOS, current mode, voltage mode | en |
| dc.title | Design of Low Power and High Speed Sense Amplifier | en |
| dc.type | Thesis | en |