Simulation study of hybrid MOSFET device architecture

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This work presents the simulation study of tunnel FET and hybrid MOSFET device architecture. As the device dimensions are shrinking and lower supply voltage is becoming the prime requirement for today's integrated circuits, the leakage current is increasing and it leads to standing power dissipation in MOSFET devices. For digital application low subthreshold swing and high Ion/Ioff is a major requirement. MOSFET based devices have a fundamental lower limit of 60 mV/decade on subthreshold swing and the leakage current is also increases with the scaling of channel length. The Double Gate MOSFET, Fin-FET, Tri-Gate MOSFET have a better control over the leakage current but the minimum limit on subthreshold swing is still a problem. Tunnel FET based devices have a different operating principle and have no lower limit of 60 mV/decade on subthreshold swing. Tunnel FET devices operate on the principle of tunneling for creating the conducting channel. In tunnel FET both the source and drain junctions are reversed biased, so the leakage current is less. The supply voltage requirement for tunnel FET is also low and it leads to lower power dissipation. The low subthreshold swing is an attracting feature for the switching kind of applications. Although the tunnel FETs have low leakage current and lower subthreshold swing, but it also have the lower value of Ion current and is not a symmetric device like MOSFET. Tunnel FET have ambipolar behaviour and have fabrication issues for complex device architectures. Today's high performance devices need high Ion/Ioff ratio and lower subthreshold swing value. Tunnel FETs are suitable only for low performance applications and for high performance applications there is strong requirement of new device architectures. In hybrid MOSFET device architecture the tunnel FET and MOSFET are combined on the same device, so that both the high Ion/Ioff ratio and lower value of subthreshold swing can be obtained. From simulation results of hybrid MOSFET device architecture, the Ion/Ioff ratio of 4.19 × 107, and average subthreshold swing value of 48.9 mV/decade have been achieved.

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Master of Technology (VLSI)

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