Reliability Issues and their Analysis on FD-SOI Standard Cell Library

Abstract

The semiconductor industry has made extraordinary advancement in the fields of research and innovation. The ever increasing customer demands have greatly challenged the semiconductor business. The semiconductor industry needs to meet the PPA (performance, power and area) requirements along with fulfilling the speed and cost requirements. To meet the standards, technology (transistor geometries) have been scaled down tremendously. Transistor architectures used over the last couple of decades like the “Bulk technology” at around 20nm have been scaled down to their last feasible physical limits. Scaling the bulk technology beyond this limit hindered the proper functioning of the transistors due to overlapping of electric fields. Therefore, it was not practical to manufacture an economically and functionally feasible transistor beyond 20nm. New technologies like FINFET and FD-SOI make the transistors better in terms of functionality and performance. However, they still suffer from reliability issues which need proper attention. This work therefore analyzes the impact of two such unreliability issues namely Bias temperature instability and Hot carrier injection effects on standard library cells. Together these phenomena are termed as ageing phenomena and the degradation caused due to these phenomena is known as ageing. The work also focuses on the asymmetric impact of these effects on the cell’s/gate’s rise and fall delays. Also the individual impact of BTI and HCI is studied and the increase in the threshold voltage of PFET and NFET is calculated. The work also investigates channel length dependency of the above mentioned effects. Finally, we observe the asymmetric impact of ageing where BTI individually in comparison to HCI leads to more degradation in delay. Also the threshold voltage of NFET’s and PFET’s see a significant increase in the values. Therefore, this study will be of help to the designers to understand the issues in reliability, the shift in transistor parameters which may lead to violation of timings and help designers decide the exact design margins by considering ageing during designing.