Study the Performance Analysis of Carbon Nanotube as a VLSI Interconnect.

Abstract

ABSTRACT Interconnect delay is a major factor determining the performance of VLSI circuits. As technology scaled down interconnects delay dominates the gate delay. In deep submicron meter VLSI technologies, it has become increasingly difficult for conventional copper based electrical interconnect to satisfy the design requirements of delay, power and bandwidth. Promising candidate to solve this problem is carbon nanotube(CNT). CNTs are susceptible to electromigration problems that plague the copper interconnect. Due to high thermal conductivity and large current carrying capacity CNTs are preferred over copper as VLSI future interconnect. In this thesis Performance of CNT and copper has been studied with equivalent circuit model of CNT and Copper at 32nm technology node. Using this model, the performance of CNT-bundle interconnects (at local, intermediate and global levels) is compared to copper wires. It is shown that CNT bundles gives better results at semiglobal and global length of interconnects whereas copper interconnect gives better result at local length of interconnects.