Low Voltage Low Power High Performance Analog C-MOS Design

Abstract

The contemporary Electronics scenario witnesses a thrust to achieve excellence in the performance of circuits while still optimizing on their ever shrinking sizes. Modern day consumer electronics has bestowed its consumers with these tiny mobile electronic gadgets for fast computation and communication. Power consumption has spurt up as a major issue where the urge is for reducing the power consumption to enhance the mobility of these circuits especially in areas such as communications where Laptops and mobile communication diaries have captivated the market. Communications has witnessed a revolutionary change over the years and still has to be explored in abundance to which VLSI circuits serve as a boon. Communications has been the major arena for the development of the high performance low power mobile circuits.Operational Amplifier is an indispensable major building block in the circuits and we have witnessed a consistent effort to enhance their performance with fruitful results optimizing on various parameters namely:" Av Amplification (Gain) " ICMR Common mode Input range " PSRR Power Supply Rejection Ratio " CMRR Common Mode Rejection Ratio " SR Slew Rate An Introduction to differential amplifier and its various parameters has been presented in the first chapter. Starting with the Earliest Op-Amp (Conventional two stage differential Amplifier) and building up hierarchically to the modern day high performance architectures various designs have been discussed and analyzed in the Second chapter.A complete description of the modern day low power Op-Amp Architectures and the proposed designs has been presented in chapter Three. The design Approaches for some Important configurations have been developed and accounted for. Finally the design results have been compared to the existing ones where the optimization can be clearly seen in certain parameters. The Op-Amp's designed are as follows:" Conventional Two Stage Op-Amp " Folded Cascode Amplifier " Constant Transconductance Input Stage " Constant Transconductance Input Stage differential Amplifier with level shifters where the major concern was reduced power, high gain, rich ICMR often required in mobile communications. The explicit results can be witnessed in chapter five, simulations carried out in Tanner Pro with the charts displaying bode plots and Transconductance plots attached towards the end of the chapter. An improvement in the positive common mode voltage is seen as compared to the existing design while still operating under low voltage maintaining reasonable gain resulting in very low power dissipation as compared to the conventional design. The constant Transconductance stage also shows good results where the performance related to the above discussed parameters has been displayed. As always there is a room for improvement to this design optimizing on various other parameters that have not been accounted for, say PSRR, CMRR etc.