Temperature Dependent Performance Analysis of Mixed-MWCNT Bundle as VLSI Interconnects

Abstract

Since 1970, the functionality and performance of integrated circuits (ICs) have been improving year after year at scaled-down technology nodes. The complexity of ICs increase because of increasing the number of functional blocks per chip. The functional blocks per IC increase, which accumulate a large area of a chip because the number of active and passive components is also increased. Thus, the dimensions of components need to be minimized to fabricate a large number of active and passive components on a single-chip. The size of the device gets minimum; however, high speed of operation and less power consumption required for high-performance ICs. For scaled-down technology nodes, the size of VLSI-IC reduces by minimizing the size of active and passive components and the size of interconnects. Interconnect is a thin conducting line, which provides the path to various parts of the IC such as power supply, ground, input signal and clock pulse. At nanotechnology nodes, the performance of IC dominates by the interconnect length and material is used as VLSI interconnect. The conventional copper (Cu) material is used as interconnect for high-performance VLSI-IC design. However, Cu has few significant issues at scaled-down technology nodes (particularly below 45nm), which is reported in the literature. These issues are low current density, short mean free path (MFP) and high resistivity at deep submicron (DSM) technology nodes. Therefore, replacing the Cu with new material at DSM technology nodes is necessary. Carbon nanotube (CNT) has been discovered as new conducting material. It may be considered as a good candidate to replace Cu interconnect because CNT has high current density, long MFP and low resistivity at DSM technology nodes. CNT is made-up of a graphene sheet rolling into a cylinder. CNTs are classified as single-walled CNT (SWCNT) and multi-walled CNT (MWCNT). SWCNT is developed by rolling a single sheet of graphene into a cylinder with a diameter of few to several nm. However, MWCNT is made up of rolling two or more graphene sheets into the cylinder, concentrically. The fabricated MWCNT has a diameter ranging from a few to several tens of nm. In the literature, various CNT bundles are proposed such as Mixed-CNT, MWCNT and SWCNT bundles, which are considered as interconnect for VLSI-ICs design. Further, bundles of SWCNT have several SWCNT with a fixed diameter, which is difficult to fabricate because there is no control on the growth process as compared to MWCNT. The modeling of MWCNT is complex as compared to SWCNT bundles because MWCNT has a various number of individual shells and each shell has a different diameter. In contrast, SWCNT bundles have only a single shell of fixed diameter. Further, the Mixed-MWCNT (MMT) bundle is established for VLSI interconnect at DSM technology nodes, which is a mixer of two or more differently-sized MWCNTs. The relative bundle is denser than MWCNT bundle because some MWCNTs of small diameter are inserted into the vacant space at side wall, corner and four adjacent MWCNTs. Thus, the conductivity of MMT increased as compared to MWCNT bundle because MMT has a large number of conducting channels. The performance of MMT as a VLSI interconnect needs to calculate the actual performance for global level interconnects at DSM technology nodes. This thesis work presents the proposed MMT nanostructure as VLSI interconnect at DSM technology nodes. The proposed MMT has two types of MWCNTs of different diameters such as MWCNTL (means large-diameter MWCNT) and MWCNTS (denotes small diameter MWCNT), which is considered as global interconnect for DSM technology nodes. The parasitic of MMT is examined by writing the analytical equations in MATLAB tool to develop the equivalent single-conductor (ESC) model. The resistance of MMT nanostructure is obtained for global level interconnect at 32, 22 and 16nm technology nodes. The resistance of MMT increases with increasing length from 400 to 2000μm and also increases for scaled technology nodes. Further, the developed ESC model of MMT nanostructure as global interconnect length is considered to examine the performance in terms of delay, power and PDP at DSM technology nodes. Similarly, the ESC model of Cu interconnect has also been developed to examine the performance of parameters under consideration for MMT nanostructure at technology nodes such as 32, 22 and 16nm. It reveals that the performance of MMT nanostructure outperforms Cu at DSM technology nodes for global level interconnect. A variable temperature influences the performance of VLSI interconnect at DSM technology nodes. Therefore, the impact of temperature on the performance of MMT interconnect needs calculation to understand the actual performance under various thermal conditions at DSM technology nodes. Temperature-dependent ESC model of MMT nanostructure as global interconnect length is developed at DSM technology nodes viz. 32, 22 and 16nm for temperature range (200-450K). The mathematical equations are derived to obtain the parasitic of MMT interconnect, which is influenced by a variable temperature range (200-450K). The parasitic of the MMT interconnect is calculated under various thermally-aware factors for variable environmental conditions at DSM technology nodes. These factors are due to electron-phonon scattering, which results from grain boundary and surface scattering of MMT nanostructure at DSM technology nodes. The MMT interconnect consists of two types of scattering-electron-phonon and electron-electron scattering. The electron-phonon scattering shows a significant impact on their parasitic; however, electron-electron scattering phenomena have a negligible impact on overall scattering phenomena. This temperature-dependent scattering influence the MFP of MMT nanostructure, which further affects the impedance parameters. Temperature-dependent parasitic of MMT nanostructure is developed and analyzed at DSM technology nodes. Temperature-dependent resistance of MMT interconnect is compared with temperature-independent resistance on a variable temperature range between 200 and 450K at DSM technology nodes. The temperature-dependent impedance parameters are used to calculate the performance such as delay, power and PDP of the proposed MMT nanostructure. The calculated performance of MMT for global interconnect length in terms of delay, power and PDP are analyzed and compared at DSM technology nodes on a variable temperature range (200-450K). Similarly, temperature-dependent ESC models of MWCNTB, SWCNTB and Cu nanostructure as global level interconnect (1000μm) are presented to obtain the performance parameters for MMT nanostructure at DSM technology nodes. Further, the developed ESC models of MWCNTB, SWCNTB and Cu are simulated with the help of the SPICE tool to evaluate the performance at DSM technology nodes. The obtained results for SWCNTB, MWCNTB and Cu are compared with MMT interconnect results at DSM technology nodes on the variable temperature range. The comparative analysis shows that the performance of MMT nanostructure performs better than Cu, SWCNTB and MWCNTB as global level VLSI interconnect at DSM technology nodes (32, 22 and 16nm) for the entire temperature range (200-450K). It reveals that the performance of MMT nanostructure outperforms Cu, SWCNTB and MWCNTB as global level VLSI interconnect length on a variable temperature range (200-450K) at DSM technology nodes viz. 32, 22, and 16nm. The MMT nanostructure may be used as a global level VLSI interconnect at DSM technology nodes under thermally-aware environmental conditions.