Design Verification Using Formal Techniques

Abstract

The increasing complexity of chips has made traditional verification methods more difficult and expensive. To tackle the challenge of accurately implementing intricate designs, current research is exploring the integration of formal techniques with adjustments to design methodologies. It has been suggested that formalizing abstract models early in the design phase can help detect design errors and reduce the cost of fixing bugs. Recognizing that different verification issues require unique strategies is crucial for effectively applying formal verification in the initial stages of design. Each perspective offers a distinct way of reasoning to answer the question, "Why is the design correct?" By employing various models and tools for each perspective, a set of viewpoints can capture the design intuition. This approach allows the models to be sufficiently small for quick construction, validation, and modification. Identifying corner case issues early in the design process results in lower redesign costs compared to discovering bugs later on. Additionally, this thesis includes efforts to cut the number of test cases in half, thereby saving simulation time. The conclusion and future directions of the work are discussed at the end of the thesis.