Synthesis of Analog IC Building Blocks

Abstract

A new methodology based on the concept of figure of merit that includes the three performance parameters, namely input-referred noise, differential dc voltage gain and unity-gain bandwidth, has been proposed for synthesizing optimal performance differential input-stage amplifiers and second stage amplifier under the constraints of area. This concept has been validated with examples both at low and medium frequencies. The four different figures of merit proposed for different structures and in different frequency domains peak at certain values of relative area allocation to the input transistors in the range of 62 % to 92 % of the available area. The peak achievable value of the figure of merit is a function of both area and power. However, at low frequencies, it is independent of biasing current (and hence power) subject to a minimum current (and hence a minimum power) required to keep all the transistors biased in the saturation region. It is observed that the differential dc voltage gain, unity-gain bandwidth and input-referred noise achieved at peak figure of merit are very close to their best individually achievable values. The study also highlights that the total band noise for a given area is practically independent of relative allocation of areas between the input and load transistors and also does not vary significantly with the total area assigned to the circuit at medium frequencies. Incorporating the above ideas, a CAD tool has been developed in C/C++, for the synthesis of differential amplifiers. The tool has been tested for 2400 design-syntheses with dc power varying from 100 µW to 1000 µW, differential dc voltage gain in the range of 10 – 1000 V/V, unity-gain bandwidth in the range of 1 – 100 MHz, and input-referred noise in the range of 1 – 20 nV/rtHz. The synthesized circuits are mainly governed by power and noise. At a constant power, area required increases exponentially with the requirement of reduced input-referred noise. Area requirement can also be reduced at the cost of increased power consumption and reduced differential dc voltage gain for the same input-referred noise. Hence, a clear Area – Power tradeoff is seen in the synthesized designs. The layouts of some of the synthesized circuits were drawn manually in 1.2 µm CMOS technology and were simulated and compared against the simulated results on schematics for final validation of the synthesis tool. The limits and limiting relationships on differential dc voltage gain, and Unity-Gain Bandwidth, of an unloaded differential amplifier were explored. It has been observed that the product of an unloaded differential amplifier is a technology constant.