Study the subthreshold logic design

Abstract

In this report, an equivalent RC delay approach to study the subthreshold operation for inverter, AND logic and OR logic circuits is presented. In these subthreshold circuits, the supply voltage is below the threshold voltage of the device. The symmetric inverter is designed for subthreshold current model, which is exponential in nature and is a more accurate model which considers the effect of thermal energy on the Boltzmann distribution of electron energies. Based on the inverter, the other static circuits and domino circuits are designed and various bulk biasing schemes are used. Taking the effect of miller capacitance, equivalent capacitance is calculated. The average resistance is also calculated for each circuit and based on this, the 90% delay is calculated for each case. The results of RC delay are compared with SPICE simulation in 32nm technology. The results reveal the domino OR type 4 has least delay among all domino OR circuits and AND type 1 has least delay among all domino AND circuits. This is due to the fact that these circuits have least output capacitances. Comparison on the basis of Power Delay Product (PDP) is also done for all the circuits in subthreshold regime. Domino OR type 2 and domino AND type 2 are more efficient due to the lower value of the power delay product.