Low-Voltage CMOS Analog Multipliers
| dc.contributor.author | Kumar, P. Mohan | |
| dc.contributor.supervisor | Pandey, Rishikesh | |
| dc.date.accessioned | 2011-12-09T07:34:21Z | |
| dc.date.available | 2011-12-09T07:34:21Z | |
| dc.date.issued | 2011-08-09 | |
| dc.description | M.Tech. (VLSI Design and CAD) | en |
| dc.description.abstract | Real-time analog multiplication of two signals is one of the most important operations in analog signal processing. Multiplier is such an important element which contributes substantially to the total power consumption of the system. On VLSI level, the area also becomes quite important as more area means more system cost. Speed is another key parameter while designing a multiplier for a specific application. These three parameters power, area and speed are always traded off. The multiplier is used not only as a computational building block but also as a programming element in systems such as filters, neural networks, and as mixers and modulators in a communication system. Different multipliers based on different topologies such as V-I convertor, differential amplifier, summing and squaring circuits, etc have been discussed. These structures of multipliers have been simulated using spectre (Cadence) tool. The simulation results of the multiplier presented in this thesis have been compared which confirm the effectiveness of the circuits. | en |
| dc.format.extent | 2030510 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/10266/1582 | |
| dc.language.iso | en | en |
| dc.subject | Analog Multiplier | en |
| dc.title | Low-Voltage CMOS Analog Multipliers | en |
| dc.type | Thesis | en |
