Pipelined Analog to Digital Converter - Study and Design

Abstract

The main objective of this dissertation is to study and design pipelined ADC which offers attractive combination of high-speed, high-accuracy and low power consumption. With the advancement of Deep Sub-micron (DSM) technology, the low power supply became the trend of circuit designing. However, signal dynamic range decreases due to the reduction in the supply voltage which gives challenge to circuit designers to restore the dynamic range along with the reduction of noise and signal distortion. This work is divided in two parts: First, study of Pipelined Analog to Digital Converter to study the accuracy and various errors in pipelined ADC. Second, is its design for accuracy with low power. A resolution of 8-bit and 30 MS/sec sampling rate is chosen targeting the applications in Wireless Local Area Network (WLAN) and Wide Area Network (WAN). The design was simulated in UMC 0.18 μm Mixed Mode CMOS 1P6M process with power supply of 1.8V in Cadence Analog Design environment.