Design of CMOS low drop-out regulator with improved PSRR

Abstract

The advancement in battery operated portable devices, noise sensitive devices and other devices, which need high precision supply voltages has fuelled the growth of Low Drop-Out Regulators. Low Drop-Out Regulators showed advantage over its counterpart. The design of Low Drop-Out Regulators with high performance is challenging problem now-a-days. The increasing demand, however, is especially apparent in mobile battery operated products, such as cellular phones, pagers, camera recorders and laptops. In this dissertation, A CMOS Low Drop-out Regulator with Improved PSRR is proposed. The proposed circuit is developed using error amplifier, subtractor circuit and PMOS as pass device. For the improvement of dc PSRR, a subtractor circuit is introduced along with two stage error amplifier with NMOS mirror load in conventional low drop-out regulator topology. The proposed circuit is simulated using TSMC 0.18μm CMOS technology process parameters and the simulation results are presented. The layout of the compensated error amplifier is designed using Cadence Virtuoso XL Design Environment tool. The performance parameters of the proposed LDO has also been compared with the existing LDO circuits available in literature and the comparison shows that the proposed LDO has wider range of PSRR with better dc PSRR.