Topology And PWM Technique Design Of Z-Source Inverters

Abstract

The single-stage buck-boost inverter (DC-AC conversion) technology together with the two-level (2L) and multilevel output voltage topologies has a wide area of applications such as electric drives, distributed power generation (wind, PV, fuel cell, etc.), FACT devices, and electric vehicles. The continuous improvements in this technology strengthen its position in the above mentioned applications. The concept of Z source inverter (ZSI) is most popular in the single-stage buck-boost inverter technology. As compared to the voltage source inverters (VSI), the concept of ZSI offers increased reliability because the impedance network used in ZSIs eliminates the chances of direct short-circuiting of input dc source during turn on/off transitions of power switches of the same phase leg. Therefore, the dead time requirements are nil in ZSIs. However, the concept of ZSI still requires to be explored in its various aspects such as the size of the impedance network (IN), implementation and analysis in multilevel DC-AC topologies, methods to increase its input-output voltage gain, and suitability to various existing PWM techniques of VSI after proper modification, etc. The research work carried out in this thesis attempt to contribute to the recent development in the field of ZSI. Starting from two-level ZSI (2L-ZSI), this research work explores the new possibilities in its PWM techniques developments. The design and experimental implementation of advanced bus clamping (ABC) PWM switching sequences in 2L-ZSI is an important contribution of this research work. It has been seen that, a properly designed space vector PWM (SVPWM) technique using ABC switching sequences reduces the size of the IN of 2L-ZSI by 34 percent as compared to the conventional PWM technique. In case of three-level ZSI (3L-ZSI), the research work starts with the implementation of the concept of ZSI in the controlled diode bridge clamped (CDBC) VSI configuration. Here, the main advantages and drawbacks of using CDBC ZSI have been highlighted. Besides, a new version of continuous SVPWM of 3L-ZSI is proposed. The proposed SVPWM switching pattern optimizes the number of switching transitions per carrier cycle and points out the dependency of the modulation index on the switching frequency of the power switches. Progressing forward to contribute further to the PWM techniques of 3L-ZSI, a modified SVPWM switching state diagram and two new reduced common-mode voltage (CMV) switching patterns iv have been proposed. Modified three-level (3L) SVPWM switching diagram offers enhanced dc bus utilization as compared to its conventional counterpart. An improved version of the maximum boost control (MBC) technique of voltage boosting has been also proposed based on the proposed modified SVPWM switching state diagram. The improved version of the MBC technique eliminates the problem of the sixth fundamental frequency ripple components of impedance network inductor current present in the existing MBC of voltage boosting. The proposed reduced CMV switching patterns offer the reduced size of the IN while limiting the CMV magnitude to one-sixth of the available dc-link voltage. The above mentioned research work is successfully validated using theoretical findings, simulation, and experimental results. Lastly, for the application of an isolated PV power generation unit, a unified closed-loop control technique has been implemented in 3L-ZSI. The theoretical findings and simulation results proves the effectiveness of the unified closed-loop control technique of 3L-ZSI.