Design of 10-bit Track and Hold Circuit using Bootstrapped Switch

Abstract

Digitalization is bringing revolutionary changes in each area of modern technology like telecommunication, consumer electronic appliances etc. The role of ADCs and DACs are significant in interfacing digital electronics with analog world. The Track and Hold (T/H) Circuit is the front end of all ADCs as it ensures the accurate digitization of a constant analog value at the output terminal. A low performance T/H can degrade the performance of its subsequent circuitry. So, it is essential to have a good T/H circuit. This work presents and discusses a new architecture of a low power Opamp-less fully differential Track and Hold circuit in 180 nm CMOS technology. This circuit uses the concept of bootstrapping to achieve a constant on-resistance. With this idea, the gate-to-source voltages of transmission gate are made independent to the input signal amplitude and thus made the circuit linear. The circuit is optimized for the following performance parameters: Total Harmonic Distortion (THD), Signal-to-Noise and Distortion Ratio (SNDR), Spurious Free Dynamic Range (SFDR) and Effective Number of Bits (ENOB), Power dissipation and on-resistance. The circuit is designed to work on the maximum sampling frequency of 100MHz. For input signal of 5.3125MHz and sampling frequency of 20MHz, it achieves THD of 60.44dB with SNDR of 60.28dB. The SFDR for the proposed circuit comes out to be 60.78dB with 9.7 effective number of bits. It uses a power supply of 1.8V and dissipates power not more than 41.1dBm. All the simulations and parameter calculations are done in CADENCE ®VIRTUOSO ANALOG DESIGN ENVIRONMENT and the value of parameters are verified in MATLAB also.