Verification of Row Voltage Control Block In the NAND Flash Memory

Abstract

The correctness of a digital circuit is an important consideration in the design of digital systems. Given the extremely high and increasing costs of manufacturing microchips, the consequences of flaws getting unnoticed in system designs until after the production phase, would be very expensive. At the same time, RTL verification is still one the most challenging activities in digital system development. Different methodologies such as UVM are now majorly used for verification because of the reusability of the components in verification environment. In this project work, verification of “Row Voltage Control” module inside NAND Flash memory is done. Testing is said to have completed once 100% coverage is attained. Functional coverage model is plugged to DUT along with UVM test bench and checked for 100% coverage in “Row Voltage Control”block.