UPIO Delayline Delay Extraction Using ELDO
| dc.contributor.author | Yadav, Shaifali | |
| dc.contributor.supervisor | Faseehuddin, Mohd | |
| dc.contributor.supervisor | Kohli, Amit Kumar | |
| dc.date.accessioned | 2025-08-07T05:21:39Z | |
| dc.date.available | 2025-08-07T05:21:39Z | |
| dc.date.issued | 2025-08-04 | |
| dc.description.abstract | This report focuses on the extraction of delay in Universal Programmable Input/output (UPIO) Delayline circuits using Eldo, a high-precision SPICE simulator. The accurate determination of delay characteristics in UPIO Delaylines is essential for the performance and reliability of high-speed digital circuits. The study begins with an overview of the importance of delay lines in digital circuit design and the specific applications of UPIO Delaylines. It then outlines the theoretical foundations of delay extraction, emphasizing the critical parameters and metrics that influence delay performance. The methodology section details the simulation setup, including the configuration of the Eldo simulator, the design of test benches, and the simulation conditions. It provides a step-by-step guide for setting up the Eldo environment, running simulations, and extracting delay data to ensure precision and reproducibility. Simulation results are presented and analyzed, illustrating the delay characteristics of the UPIO Delayline under various operating conditions. The report compares the simulated results with theoretical predictions and discusses any observed discrepancies. In this report, we present a novel method for extracting resistance values in electronic circuits using a custom routing approach. The accurate extraction of resistance values is crucial for ensuring the performance and reliability of electronic designs, particularly in high-speed and high-frequency applications where precise impedance control is necessary. Our method involves the development of a custom routing algorithm that not only optimizes the physical layout of the circuit but also accurately calculates the resistance values of the interconnects. The algorithm takes into account various factors such as wire length, cross-sectional area, and material properties to compute the resistance. Additionally, it integrates seamlessly with existing electronic design automation (EDA) tools, providing a comprehensive solution for designers. | en_US |
| dc.identifier.uri | http://hdl.handle.net/10266/7061 | |
| dc.language.iso | en | en_US |
| dc.publisher | Thapar Institute of Engineering and Technology | en_US |
| dc.subject | Delay | en_US |
| dc.subject | ELDO | en_US |
| dc.subject | Extraction | en_US |
| dc.subject | Digital | en_US |
| dc.subject | UPIO | en_US |
| dc.title | UPIO Delayline Delay Extraction Using ELDO | en_US |
| dc.type | Thesis | en_US |
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