Design and implementation of efficient adder based floating point multiplier

Abstract

Multipliers are widely used in DSP processors, filters, communications systems etc. A high speed multiplier is always desirable. Floating point numbers provide larger range and better accuracy than fixed point numbers. In fixed point number representation, digits after and before the decimal is fixed while in floating representation the decimal point is not fixed, it can float. Floating point multipliers are used for calculating product of two floating point numbers. There are different steps involved in calculation of product of two floating point numbers. The major steps involved are calculation of sign, significand and exponent. For the significand, adders are required for accumulating the partial products. Adders are also used in calculation of exponent. The maximum time of multiplication is elapsed in accumulating the partial product and at the final addition stage to get the significand product. So, the multiplication time can be reduced if the partial products are accumulated with the help of fast adders.

This thesis aims to implement a single precision floating point multiplier using the fastest adder. For this, initially different adders are compared in terms of delay and then on the basis of the results obtained, the floating point multiplier is designed using the fastest adder. The multiplier is also designed using different adders at its different stages and their results are compared on the basis of delay and area. The modules have been designed in Verilog HDL, simulated and synthesized using Xilinx 14.5.