Methodology For Designing High Speed Reconfigurable Custom Computer

Abstract

Reconfigurable Custom Computers are being proposed as faster means of devices for Application specific computing. A key difference between the classical computer and a Reconfigurable custom computer is that a classical computer solves a problem with the available hardware and/ or logic whereas a custom computer solves the problem with specialized hardware and/ or logic. As an emerging field Reconfigurable Custom Computing is emerging as an important new organizational structure for implementing computations on the best-fit hardware and/ or best-fit logic. It combines the post-fabrication programmability of processors with the spatial computational style most commonly employed in hardware and logic designs. The result changes traditional “hardware” and/ or “software” boundaries, providing an opportunity for greater computational capacity and density within a programmable media. Reconfigurable Computing must leverage traditional CAD technology for building spatial designs. Specifically we are interested in questions: Can a Reconfigurable custom computer be Applicable to every problem where a classical computer can be used? Is it a costly affair to solve a problem using Reconfigurable custom computer? And also does the Logic selection play a vital role in solving a particular problem? If so, which, why, and how? For answering the above questions we analyzed the fields in which Reconfigurable Custom Computing can be applicable, then the ways in which the Reconfiguration can be done, the technologies/ resources needed and also the parameters that need to be taken into consideration while selecting the logic in an RCC (Reconfigurable Custom Computing) for solving a particular problem. Here we restrict our thesis work in suggesting an algorithm in selecting an appropriate logic for the specified problem. Logic in this sense means algorithm. In this thesis, we assume an architecture, which has a VLISVM (Very Large Instruction Set Virtual Machine), which can support all possible instructions. We have a Root machine, which has the compiler for compiling the instruction set in the VLISVM. The root machine identifies the Operation, which can be solved using a reconfigurable custom made computing mechanism. Once it identifies the Operation it selects the needed Instruction set from the VLISVM. Now hardware software partitioning will be done in which it has to decide which part will be implemented in the hardware and which will run above it. Now our work suggests which hardware topology or architecture will be well suited for implementing a particular operation amongst the various options available. Because the Hardware topology and computation topology is modified by reallocating the resources to computation. While suggesting the Architecture various parameters have to be taken into consideration like the priority to be given to the selected problem and the amount of resources available in terms of RAM where the Reconfigured architecture will be downloaded. Obviously the selection of logic, to be implemented as the new hardware architecture plays a vital role because of the reason that a problem can be solved in various ways using various architectural logics. We have taken a small example and tried to solve using various logics, and also attention has been given in the selection of the type of logic. We focus on the Reconfiguration part and the one used will be of the category, Architectural reconfiguration. This Method of reconfiguration will be Coarse grained because the reconfiguration is merely the programming the interconnections between fixed blocks. No reconfiguration in terms of transistors gates and registers.