Performance Analysis of FinFET based SRAM at Nano-scaled Technology Nodes

Abstract

SRAM is widely used type of memories in low powered consumer electronics. In fact, the majority of transistors found in many integrated circuits are those utilized in the SRAM bit cells with the percentage die occupied by this type of memory approaching 85%-90% integrated circuits. With the rise in demand for the low power high-speed devices, like smartphones and tablets, and the emergence of IoT devices, the need for scaling down SRAM has become a necessity. Since SRAM is typically constructed from traditional CMOS devices, all of the issues associated with MOSFET scaling are applicable to scaling of SRAM. This work focuses on the study of the 6T FinFET SRAM, its advantages and disadvantages over MOSFET based 6T SRAM and different performance metrics such as delay time, power delay product (PDP) and static noise margin (SNM). A standard 6T SRAM cell is realized using predictive technology models (PTM) at 7nm, 10nm, 14nm ,16nm and 20nm technology nodes. These are evaluated and compared for previously mentioned performance metrics. Furthermore, the SRAM cell was power gated using fine grain gating technique and then compared with standard cell SRAM. The goal is to identify the trends for different parameters at different technology nodes. The models were then simulated in a variable temperature environment. The results conclude that the 7nm FinFET SRAM cells performs better at all aspects and the most resilient under variable temperature, as suggested theoretically, followed by SRAM cells at 10nm ,14nm, 16nm and 20nm nodes. It was also concluded that the gated versions of SRAM cells perform poorly then their standard counter parts but have improved PDP and lower power dissipation.