FPGA Implementation of EEAS Cordic based Sine and Cosine Generator

Abstract

With increasing on-chip complexities the on-chip area is a major concern. Today users desire every gadget to be smaller in size, mainly the handheld systems. So researchers keep on exploring for the methods to minimize the on chip area. They have to constantly muddle through speed area trade-off. CORDIC is one such kind of algorithm. The CORDIC algorithm has become a widely used approach to elementary function evaluation when silicon area is a primary constraint. The implementation of CORDIC algorithm requires less complex hardware than the conventional DSP methods. CORDIC is far more economical compared to DSP algorithms in terms of area and power consumption. The main benefit of this algorithm is its flexibility. Even if the speed of the system implemented using basic CORDIC degrades, but it can be easily adjusted by introducing few modifications as discussed in this thesis. The scope of this thesis includes study of VHDL for the design of EEAS CORDIC algorithm to generate basic trigonometric functions along with validations using implementation on FPGA with the design interfaced to the LCD to view the results.