Design of High Performance Frequency Divider

Abstract

The frequency divider is an important building block in today’s high speed circuits because it is an integral part of the phased locked loop employed in frequency synthesizer to generate frequencies from a single stable reference frequency. Mostly a crystal oscillator is used for the reference frequency. Most of the frequency synthesizer employs a Phase Locked Loops circuit, as this technique offer many advantages such as minimum complex architecture, low power consumption and a maximum use of Large Scale Integration technology. There are many designs in communication that require frequency synthesizer to generate a range of frequencies; such as cordless telephones, mobile radios and other wireless products. The accuracy of the required frequencies is very important in these designs as the performance is based on this parameter. One approach to this necessity could be to use crystal oscillators. It is not only impractical, but is impossible to use an array of crystal oscillators for multiple frequencies. Therefore some other techniques must be used to circumvent the problem. The main benefit of using Phase Locked Loop technique in frequency synthesizer is that it can generate frequencies comparable to the accuracy of a crystal oscillator and offer other advantages mentioned previously. Considering the scope of the frequency divider, this work is devoted to the designing of an efficient frequency divider. Which can be employed in frequency synthesizer using phase locked loop technique. The work embodied the designing of divide by 64, divide by 65 prescalers, swallow counter to count down from the loaded number to zero, Main counters and a control unit to govern the operations of sub-functional units employed in final design of frequency divider.