Linear feedback shift registers in wireless communication systems

Abstract

The field of wireless communications is currently growing at an unprecedented rate. This growth, prompted in part by the demand for more high-speed, broadband communication systems, has led to the need for high-resolution, broadband wireless measurement equipment. The mobile communication system is one of the most important phenomenon in the history of telecommunication which has enriched human civilization and mankind by bringing business and community together.. In Spread Spectrum CDMA (SS-CDMA) system each user is assigned a pseudo noise (PN) sequence for the purpose of spreading as well as dispreading. Thus PN-sequence generation is considered to be the heart of SS-CDMA system. The maximal length PN-sequence (m-sequence) is the bestknown best-described PN-sequence whose length is equal to its period. Various PN-codes can be generated using Linear Feedback Shift Register (LFSR).The generator polynomial provides the necessary feedback taps for the LFSR circuit. The implementation of the LFSR circuit with VLSI technology makes it useful in low-power communication system design. LFSR is basically, a shift register configuration that propagates the stored patterns from left to right. The modification that provides the PRBS generation is due to the XOR feedback of the selected flip-flop outputs, named taps. When the taps are chosen properly, the LFSR will traverse through all possible states except for the all 0s state and will produce a maximum length PRBS sequence named M-sequence. In order for the desired operation, the LFSR should be first initialized to a well-known stage, which is usually referred to as seed. For an n stage LFSR, there are 2n-1 states, and the Msequence is 2n-1 bits long. Hence, the M-sequence is periodic, and after the 2n-1 distinct values, it repeats itself in the next samples. Thus the linear feedback shift register (LFSR) is a shift register which, using feedback, modifies itself on each rising edge of the clock. The feedback causes the value in the shift register to cycle through a set of unique values. The choice of LFSR length, gate type, LFSR type, maximum length logic, and tap positions allows the user to control the implementation and feedback of the LFSR, which, in turn, controls the sequence of repeating values the LFSR will iterate through. Linear Feedback Shift Registers (LFSRs) are a fundamental function in applications such as pseudo-random noise (PN) generators, RS Code Generators and BIST(Build in Self Test). PN generators are at the heart of every spread spectrum system, and are a good example for demonstrating how you can dramatically reduce FPGA utilization by exploiting the Virtex SRL. In a CDMA system, many PN generators are needed to distinguish channels, base stations, and handsets. You can achieve extremely efficient LFSR implementations by using the Virtex Shift Register LUT (SRL). Though the mathematics behind a PN code can be extremely complicated, the LFSR implementation can be relatively simple. Another application of LFSR includes RS-Code Generator. RS code generators are used extensively in Code Division Multiple Access (CDMA) systems to generate code sequences with good correlation properties. The RS code generators use efficiently implemented Linear Feedback Shift Registers (LFSRs) in both the Virtex/Virtex-II series and Spartan-II family using the SRL16 macro. LFSR’s are also used as a important building block in Build in Self Test (BIST) Generation. Built-in self-test (BIST) techniques enable an integrated circuit (IC) to test itself. BIST reduces test and maintenance costs for an IC by eliminating the need for expensive test equipment and by allowing fast location of failed ICs in a system. BIST also allows an IC to be tested at its normal operating speed which is very important for detecting timing faults. Despite all of these advantages, BIST has seen limited use in industry because of area and performance overhead and increased design time. This dissertation presents automated techniques for implementing BIST in a way that minimizes area and performance overhead.