Design and Implementation of a 32-Bit MAC Unit with Pipelined Variable Stage Carry Select Adder

Abstract

The addition and multiplication of two binary numbers is the fundamental and most often used arithmetic operation in microprocessors, digital signal processors, and data-processing application-specific integrated circuits. At the heart of data-path and addressing units in turn are arithmetic units, such as comparators, adders, and multipliers. Since multiplication dominates the execution time of most DSP algorithms, so there is a need of high speed multiplier. This MAC(Multiplier and Accumulator Unit) with 1 multiplier and 1 accumulator.The multiplier is composed of Booth encoder block, wallace tree, 64 bit carry select adder block. In 32bit × 32 bit multiplication, we have used modified Radix-4 Booth's algorithm where outputs of encoding block are partial products and additional 1bit signal were added to Wallace tree. By implementing Wallace tree with 4:2 CSA improves the regularity because c_out is independent to c_in. In fact, each stage acts at the same time. The final result is the sum of carry and the sum vector through 64bit carry select adder. The output of multiplier is accumulated by the accumulator and we used 64bit carry select adder in the accumulator. Different adder architectures like Carry Chain Adder, Carry- look Ahead Adder, Carry Select Adder and Carry Skip Adder for different operand size like 16-bit,32-bit and 64-bit, are simulated and synthesized on FPGA using Xilinx ISE. On the basis of their synthesized results, one of the adder which have less delay and minimum area (Carry Select Adder) is chosen. A 32-bit Pipelined Booth Wallace MAC Unit is designed in which the multiplication is done using the Modified Booth Wallace Multiplier and in the final stage addition of multiplier and in accumulator the Pipelined Variable Stage Carry Select Adder is used and the pipelining is done in the Booth Multiplier and Wallace Tree.

MAC unit is described in VHDL and synthesized the circuit using 90 nm standard cell library on FPGA. This MAC Unit (with Pipelined Variable Stage Carry select adder in the final stage of multiplication and accumulator)has higher speed than conventional or non pipelined Booth Wallace MAC and Pipelined Booth Wallace MAC (with non-pipelined Carry Select Adder).